1. Field of the Invention
The present invention relates to a frequency multiplier. In particular, the invention relates to a frequency multiplier that is used in radio communication equipment and is capable of switching the output frequency.
2. Description of the Related Art
Nowadays, with the number of transmission carrier frequency bands increases for more effective use of frequencies, radio communication equipment such as cellular phones is increasingly used in such a manner that the carrier frequency is switched. Frequency multipliers also need to be used in such a manner that switching is made as appropriate among a plurality of frequencies (multiplication numbers), and are required to be able to switch the frequency easily. On the other hand, there are no bounds to the requirements of multi-functionality and size reduction for equipment. In portable equipment such as cellular phones that are a typical example of radio communication equipment, because of its portability, not only reduction in the equipment size and weight but also reduction in the current consumption during a communication operation are an important performance index.
In conventional radio communication equipment, to obtain a plurality of necessary frequencies, frequency multipliers having prescribed multiplication numbers, respectively, are incorporated for the respective frequencies or any of circuits shown in FIGS. 15 to 17 is used.
FIG. 15 shows a frequency multiplier 100 according to a first conventional technique, which is constituted of a switch circuit 110, a limiter amplifier 120, a bandpass filter (hereinafter abbreviated as BPF) 130, and an amplifier (hereinafter abbreviated as AMP) 140.
An input frequency signal VIN having a frequency f is input to the switch circuit 110. Controlled by a control circuit (not shown), the switch circuit 110 switches as appropriate between a path for directly outputting the input frequency signal VIN as an output frequency signal VOUT and a path for multiplying the frequency by a prescribed multiplication number. The input signal VIN that has been input to the path for multiplying the frequency by a prescribed multiplication number is limited in voltage amplitude by the limiter amplifier 120 so as to be shaped into a pseudo-rectangular wave. The BPF 130 extracts a prescribed frequency component from harmonic components of the pseudo-rectangular wave. The extracted frequency component is amplified by the AMP 140, whereby an output signal VOUT having a frequency obtained by multiplying the prescribed multiplication number is produced.
FIG. 16 shows a frequency multiplier 200 according to a second conventional technique, which is constituted of a switch circuit 110 and a mixer circuit 150.
As in the case of the first conventional technique, when input to the switch circuit 110, an input frequency signal VIN having a frequency f is subjected as appropriate to switching between a path for directly outputting the input frequency signal VIN as an output frequency signal VOUT and a path for multiplying the frequency by a prescribed multiplication number under the control of a control circuit (not shown). Having the mixer circuit 150, the path for multiplying the frequency by a prescribed multiplication number performs mixing processing on the two input frequency signals VIN. That is, the mixer circuit 150 mixes the two input frequency signals VIN having the frequency f with each other and outputs a resulting signal.
FIG. 17 is a circuit diagram of a mixer circuit (frequency doubler circuit) 150A having a frequency multiplication number of 2, which is an example of the mixer circuit 150 in FIG. 16. Transistors Q101 and Q102 constitute a first differential pair. Their emitter terminal connecting point is connected to the ground GND (ground voltage) via a current source I100. The base terminals of the transistors Q101 and Q102 are DC-voltage-biased by a voltage source VB101 via respective resistors R101 and R102. An input frequency signal VIN is input to the base terminal of the transistor Q101. A capacitance C101 that is connected to the base terminal of the transistor Q102 is a grounding capacitance.
Resistance elements R103 and R104 as loads are connected to the first difference pair, Q101 and Q102. The connecting points of the resistance elements are connected to a next-stage buffer section, which is constituted of a transistor Q103, a current source I101, a transistor Q104, and a current source I102. The collector terminals (output terminals) of the first differential pair, Q101 and Q102 are connected to the base terminals of the respective transistors Q103 and Q104, whereby emitter follower circuits are formed.
A third stage to which output signals of the buffer section constitutes phase shift sections. The output terminals of the buffer section, which is constituted of the transistor Q103, the current source I101, the transistor Q104, and the current source I102, are connected to two kinds of phase shift sections, that is, a phase advancing section that is provided with a capacitance C102, a resistance element R105, a capacitance C103, and a resistance element R106 and a phase delaying section that is constituted of a resistance element R107, a capacitance C104, a resistance element R108, and a capacitance C105, whereby a phase difference of 90° is obtained. The phase advancing section is also provided with a voltage source VB 102 between the connecting point of the resistance elements R105 and R106 and the ground GND.
Output signals of the phase shift sections are input to a fourth-stage mixer section. Specifically, the output terminals of the phase advancing section that are the connecting point of the capacitance C102 and the resistance element R105 and the connecting point of the capacitance C103 and the resistance element R106 are connected to a second differential pair, Q106 and Q105 and a third differential pair, Q107 and Q108 that have opposite input/output relationships. The output terminals of the phase delaying section that are the connecting point of the resistance element R107 and the capacitance C104 and the connecting point of the resistance element R108 and the capacitance C105 are connected to a fourth differential pair, Q110 and Q109 having the second differential pair, Q106 and Q105 and the third differential pair, Q107 and Q108 as loads. The second to fourth differential pairs are biased by a current source I103 and connected to load resistance elements R109 and R110.
In the mixer section, the second differential pair, Q106 and Q105 and the third differential pair, Q107 and Q108 have opposite input/output relationships and input signals to the second differential pair, Q106 and Q105 and the third differential pair, Q107 and Q108 and input signals to the fourth differential pair, Q110 and Q109 have a phase difference of 90°. Therefore, when the input signals to the second differential pair, Q106 and Q105 and the third differential pair, Q107 and Q108 have a peak voltage difference, the input signals to the fourth differential pair, Q110 and Q109 have no voltage difference. Conversely, when the input signals to the second differential pair, Q106 and Q105 and the third differential pair, Q107 and Q108 have no voltage difference, the input signals to the fourth differential pair, Q110 and Q109 have a peak voltage difference. Therefore, an output signal of the mixer section is switched every half cycle of the input frequency signal VIN, whereby the frequency is doubled.
However, in the frequency multiplier 100 according to the first conventional technique, when an input signal VIN having only a single frequency component originally is modulated into a rectangular waveform by the limiter amplifier 120, harmonic components included in the rectangular waveform are dominated by odd-numbered harmonic components. This results in a problem that even-numbered harmonic components such as a frequency-doubled component have low signal intensity and hence are hard to extract.
Further, the BPF 130 is necessary to extract a prescribed frequency component. If the signal intensity of a frequency component to be extracted is insufficient, amplification by the AMP 140 is also needed. It is unavoidable that the circuit scale and the current consumption become large. This is problematic when the frequency multiplier 100 is applied to, for example, portable equipment such as cellular phones, because neither high-density mounting nor low power consumption can be attained.
In the frequency multiplier 200 according to the second conventional technique, to obtain a frequency-doubled output frequency signal VOUT that is free of distortion, it is necessary to adjust the phase difference between output signals of the phase advancing section and those of phase delaying section correctly to 90°. To this end, it is necessary to accurately realize characteristic values of the capacitances C102 to C105 and the resistance elements R105 to R108 that constitute the phase advancing section and the phase delaying section. However, a characteristic value of each element for realizing an optimum operation point of the mixer circuit 150A is only one point. There are problems that designing work of determining element characteristic values is cumbersome and difficult, and that the output frequency signal VOUT deviates from the optimum state because of deviations of the element characteristic values due to dispersion in manufacture, differences in temperature characteristic, etc. of each element and it is difficult to maintain a correct output frequency signal VOUT over time and over differences in temperature characteristics.
Further, in the frequency multipliers 100 and 200 according to the first and second conventional techniques, the frequency of the output frequency signal VOUT is switched by switching the path of the input frequency signal VIN by the switch circuit 110. However, the current that is consumed to drive the switch circuit 110 is not negligible. This prevents reduction of the current consumption of the frequency multipliers 100 and 200 and hence is a problem.